In the field of semiconductor devices, the frequency of operation of the devices is constantly increasing. For clocked logic devices, the time to evaluate, which is the time allotted for a logic input to propagate to a logic output, is constantly decreasing and this increases the opportunity for corruption of the data outputs of these devices. For domino circuits this problem is especially acute, since the time to evaluate is one-half of the clock period.
In domino circuits, data is received on a first transition of the clock, evaluated, and latched on the next transition of the clock. Such paths are difficult to design, since time cannot be borrowed from the previous cycle as in the case of static circuits, and, as mentioned above, the time to evaluate is one-half of the clock period.
Since the time to evaluate in a domino circuit is one-half of a clock period, the speed of a domino circuit can limit the clock frequency of the system. For example, if the output signal of a domino circuit misses the setup time to a latch by t nanoseconds and the clock period is T, then the frequency of the chip is reduced to 1/(T-2t). In contrast, for a path which does not have domino circuits, not meeting the setup time by an equal amount will reduce the frequency to 1(T-t), or only one-half the amount as for domino circuits.
Time borrowing domino circuits are known in the art, but they have several disadvantages. First, to obtain a complementary output of a domino circuit, an extra inverter and its accompanying delay is required. Second, when following a domino circuit with a multiplexor, a multiplexor delay is encountered. Each of these delays tends to slow the operation of the domino circuits and to increase the likelihood of data corruption as the frequency of operation is increased.
For these and other reasons there is a need for the present invention.